反向器延遲

module top;
wire b,a;
system_clock #10 clock1(a);

inverter121 acz(b,a);
endmodule
module inverter121(b,a);
input a;
output b;
not(b,a);
specify
specparam
Tpd_0_1=2:2:2,
Tpd_1_0=2:2:2;
(a=>b)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule
module system_clock(clk);

parameter PERIOD=100;
output clk;
reg clk;
initial
clk=1;
always
begin
#(PERIOD/10)clk=~clk;
#(PERIOD-PERIOD/10)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(PERIOD-1)$stop;
endmodule