11111

11111

負緣觸發的DUP

module top();
wire data,clk,o;

system_clock #60 clock1(data);
system_clock #30 clock1(clk);

d_prim1 d1(o, clk, data);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initialclk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

primitive d_prim1(q_out, clock, data);
output q_out;
input clock, data;
reg q_out;
table(10) 0 : ? : 0;
(10) 1 : ? : 1;
(?0) 1 : 1 : 1;
(0?) ? : ? : -;
? (??) : ? : -;
endtable
endprimitive

VERILOG剛開始的練習

module top;
wire a,b;
reg c;
system_clock #100 clock1(a);
system_clock #50 clock1(b);
always
#1 c=a&b;
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;

always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end

always@(posedge clk)
if($time>1000)#(PERIOD-1)$stop;
endmodule

全加器

module top;
wire a,b,sum,c_out,c_in;
system_clock #25 clock1(a);
system_clock #50 clock1(b);
system_clock #100 clock1(c_in);
add_full acz(sum,c_out,a,b,c_in);endmodule

module add_half_1(sum,c_out,a,b);
input a,b;output sum,c_out;
wire c_out_bar;
xor(sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule

module add_full(sum,c_out,a,b,c_in);
input a,b,c_in;output c_out,sum;
wire w1,w2,w3;
add_half_1 M1(w1,w2,a,b);
add_half_1 M2(sum,w3,w1,c_in);
or(c_out,w2,w3);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(PERIOD-1)$stop;
endmodule

四位元正確的....

module top;
wire sum1,sum2,sum3,sum4,c_out,a1,a2,a3,a4,b1,b2,b3,b4,c_in;
system_clock #25 clock1(a1);
system_clock #50 clock1(a2);
system_clock #100 clock1(a3);
system_clock #200 clock1(a4);
system_clock #200 clock1(b1);
system_clock #100 clock1(b2);
system_clock #50 clock1(b3);
system_clock #25 clock1(b4);
system_clock #5000 clock1(c_in);
add_full_4 acz(sum1,sum2,sum3,sum4,c_out,a1,a2,a3,a4,b1,b2,b3,b4,c_in);
endmodule
module add_half_1(sum,c_out,a,b);
input a,b;
output sum,c_out;wire c_out_bar;
xor(sum,a,b);nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule
module add_full(sum,c_out,a,b,c_in);
input a,b,c_in;
output c_out,sum;wire w1,w2,w3;
add_half_1 M1(w1,w2,a,b);add_half_1 M2(sum,w3,w1,c_in);
or(c_out,w2,w3);
endmodule
module add_full_4(sum1,sum2,sum3,sum4,c_out,a1,a2,a3,a4,b1,b2,b3,b4,c_in);
input a1,a2,a3,a4,b1,b2,b3,b4,c_in;
output sum1,sum2,sum3,sum4,c_out;wire w1,w2,w3;
add_full s1(sum1,w1,a1,b1,c_in);
add_full s2(sum2,w2,a2,b2,w1);
add_full s3(sum3,w3,a3,b3,w2);
add_full s4(sum4,c_out,a4,b4,w3);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(PERIOD-1)$stop;
endmodule

反向器延遲

module top;
wire b,a;
system_clock #10 clock1(a);

inverter121 acz(b,a);
endmodule
module inverter121(b,a);
input a;
output b;
not(b,a);
specify
specparam
Tpd_0_1=2:2:2,
Tpd_1_0=2:2:2;
(a=>b)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule
module system_clock(clk);

parameter PERIOD=100;
output clk;
reg clk;
initial
clk=1;
always
begin
#(PERIOD/10)clk=~clk;
#(PERIOD-PERIOD/10)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(PERIOD-1)$stop;
endmodule