module top();
wire data,clk,o;
system_clock #60 clock1(data);
system_clock #30 clock1(clk);
d_prim1 d1(o, clk, data);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initialclk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule
primitive d_prim1(q_out, clock, data);
output q_out;
input clock, data;
reg q_out;
table(10) 0 : ? : 0;
(10) 1 : ? : 1;
(?0) 1 : 1 : 1;
(0?) ? : ? : -;
? (??) : ? : -;
endtable
endprimitive
